| TUESDAY | THURSDAY | FRIDAY | |
| Week 1 | Lecture 1
Combinational and Sequential design review |
Lecture 2
Gate Delays Hazards in Combinational Networks |
Lecture 3
Flip-flop and Sequential Network Timing Tristate logic and buses |
| Week 2 | Lecture 4
Introduction to VHDL Entity, Architecture, Port statement, Concurrent signal assignment, modeling styles, component, port map |
Lecture 5
Simulation timing, Concurrent and sequential statements. process statement, VHDL sequential statements: if-then, case, wait statements. |
Lecture 6
Conditional and selected signal assignments, variables and constants |
| Week 3 | Lecture 7
Variable initialization, VHDL flip-flop models, signal attributes, arrays, VHDL operators and operator examples |
Lecture 8
for loop statement, Modeling sequential machines, VHDL functions, VHDL procedures |
Lecture 9
Packages and libraries, Example: TTL counter model, Enumerated types, Review ROM, modeling ROM with VHDL |
| Week 4 | Lecture 10
VHDL synthesis, clocked processes, unwanted latches, optimization, examples Lecture 10 solutions |
Lecture 11
Control/Datapath model for synchronous systems serial adder example |
Exam 1 |
| Week 5 | Lecture 13
FSMD design method, state graphs for controllers, multiplier example |
Lecture 14
PLA implementation, PALs, PLDs, One-hot state encoding, Traffic light controller |
No class. |
| Week 6 | Lecture 15
Complex programmable logic devices (CPLDs) and Field Programmable Gate Arrays (FPGAs) Signed multiplier, algorithm, datapath and control, SM charts |
Lecture 16
FSMD Timing, Dice game example: system architecture, development of control and datapath |
Lecture 17
Dice game example: VHDL for datapath and control, demo. |
| Week 7 | Lecture 18
FSMD Performance tradeoffs - multiplier example |
Lecture 19
Realization of controllers using microprogramming, |
Lecture 20
More microprogramming. Linked state machines |
| Week 8 | Lecture 21
Altera Flex 10K series architecture SM chart optimization. |
Exam 2
|
Lecture 22
Pipelining |
| Week 9 | Lecture 23 More pipelining, VHDL testbenches Lecture 24
|
Lecture 25
Sequential circuit testing, scan testing |
Lecture 26
Board level testing, Boundary scan, built-in self-test |
| Week 10 | Lecture 27
Design Example |
Lecture 28
Contemporary Issues in Digital Design |
Lecture 29
Review |