EE/CS-118 Week 8 Lecture 22 Outline

Pipelining datapaths

• Trade off area for increased throughput.
• Latency is often the same as non-pipelined version.
• Assembly line analogy
• Speed increase is a function of the number of pipeline stages

Multiplier example

Testing Digital Circuits

• Functional (Design) Testing
• Manufacture (Production) Testing

Design Testing - VHDL test benches

• Review digital system development flow
• VHDL simulation at several levels
• VHDL test benches can interact with VHDL model

VHDL Test Benches

• Simple combinational and finite state machines - vsim command files
• Modeling complex environments
• Example

request - acknowledge handshaking

• VHDL test bench models the environment
• Test benches can generate
• Complex data pattern and sequences
• Timing waveforms
• VHDL test benches may include the VHDL model as a structural component
• VHDL assert statment is often used to detect errors

entity test_bench_example is
end test_bench_example;            -- notice there are no inputs or output ports

architecture example of test_bench_example is

component vhdl_model
port(..... R : in std_logic;
           ack : out std_logic;
        ........)
end component;

signal R_test, ack_test : std_logic;
signal ......

begin

tester: process
wait until ack_test = '0';
R_test <= '1';
....                             -- perhaps provide other data
wait until ack_test = '1';
R_test <= '0';
.....
end process tester;

C1: vhdl_model port map (..... R_test, ack_test, ....);  -- the model

end example;
 
 
 
 
 
 
 
 
 
 
 
 

VHDL Assertion Statement

assert boolean-expression
    report string-expression
    severity severity-level;

If the boolean-expression is false, then the string-expression is displayed on the monitor along with the severity level. Severity-level can be

     note,
     warning,
     error,
     failure.

Action taken depends on the simulator.
 
 
 
 
 
 

Example - suppose VHDL model is supposed to generate data with even parity with ack_test:

wait until ack_test = '1';
parity := test_data(3) XOR test_data(2) XOR test_data(1) XOR test_data(0);
assert parity = '0'
    report "Parity Error"
    severity error;
R_test <= '0';
 
 
 
 
 
 

Also used in modeling flip-flops to check for timing problems:

check: process
begin
    wait until clk'event and clk='1';
    assert D'stable(setup_time)
        report "Setup Time Violation"
        severity error;
    wait for hold_time;
    assert D'stable(hold_time)
        report "Hold Time Violation"
        severity error;
end process check;