library ieee;
use ieee.std_logic_1164.all;

entity fsm1 is   
    port(X, CLK: in std_logic;
         Z: out std_logic);
end fsm1;

architecture synthesis of fsm1 is   
    signal state, nextstate: std_logic_vector(2 downto 0);
begin   
logic: process(X, state)
       begin   
	case state is      
            when "000" =>         
                if X='0' then Z<='0'; Nextstate<="001"; end if;
                if X='1' then Z<='0'; Nextstate<="000"; end if;
            when "001" =>
                if X='0' then Z<='0'; Nextstate<="001"; end if;
                if X='1' then Z<='0'; Nextstate<="010"; end if;
            when "010" =>
                if X='0' then Z<='0'; Nextstate<="100"; end if;
                if X='1' then Z<='0'; Nextstate<="011"; end if;
            when "011" =>
                if X='0' then Z<='1'; Nextstate<="101"; end if;
                if X='1' then Z<='0'; Nextstate<="000"; end if;
            when "100" =>
                if X='0' then Z<='0'; Nextstate<="001"; end if;
                if X='1' then Z<='1'; Nextstate<="101"; end if;
            when "101" =>
                if X='0' then Z<='1'; Nextstate<="000"; end if;
                if X='1' then Z<='1'; Nextstate<="000"; end if;
            when others => null; -- should not occur
	end case;   
    end process logic;

states: process
    begin
	wait until clk'event and clk = '0' ;
            State <= Nextstate;   
    end process states;

end synthesis;