EE/CS-118 Digital Design
Homework Assignments

Assignment #1 Roth Text Problems:
Review: Chapter 1: 1.1, 1.2 (use all NAND gates)
New stuff: Chapter 1: 1.5, 1.6, 1.8a, 1.9a, 1.11a, b (use only D flip-flops and NANDs), 1.12, 1.13, 1.14, 1.15
Note: For 1-8, 1-9, 1-11 - use as many states as you need.
Solutions to Assignment #1

Assignment #2 Roth Text Problems:
Chapter 2: 2.1, 2.2, 2.5 (note this is really 3 different VHDL descriptions), 2.9a.
Solutions to Assignment #2

Assignment #3
Roth Text Problem: 2.4
Additional Problems
Solutions to Assignment #3

Assignment #4 due Monday, Jan. 31.
Solutions to Assignment #4

Assignment #5
Roth Text Problems 3.2, 3.3a, 4.1
Solutions to Assignment #5

Assignment #6
Roth Text Problems 4.2
Additional Problems
Solutions to Assignment #6

Assignment #7
Roth Text Problems 5.3 (note: "tracing link paths" is the same procedure used to find next state equations for one-hot state assignments - this state assignment is similar to a one-hot assignment), 5.4, 5.5a,b, 5.9a,b (non-graded)
Solutions to Assignment #7

Assignment #8
Roth Text Problems 5.6 (for a, assume state = S0 at beginning of timing diagram.), 5.8a,b, 10.1, 10.2, 10.4
Solution to Assignment #8

Assignment #9
Roth Text Problems 10.6a, 11.4, 11.5
Solutions to Assignment #9