• Digital Systems Design with VHDL by Mark Zwoliński., Prentice Hall, 2000
• Rapid Prototyping of Digital Systems, A Tutorial Approach, James O. Hamblen, Michael D. Furman, Second Edition, Kluwer Academic Publishers, 2001

Week 1: Zwolinski, Chapters 1,2, 3

• Digital Design Concepts
• Modern design process - tools, implementation choices
• CMOS technology
• Programmable logic - PLDs, CPLDs, gate arrays, FPGAs
• Electrical properties - noise margins, timing, fanout
• Review combinational logic design
  • Minimization
  • Timing - logic hazards (Maxplus Exercise)
  • Number codes - 2's complement, fixed and floating point
  • Other codes - character, gray code, parity
  • Combinational logic modeling with VHDL
  • Overall structure - entity architecture
  • Syntax - identifiers, spaces, comments
  • Structural modeling - netlists
  • Maxplus Exercise

• Laboratory 1 - Learning Maxplus and ModelSim
• More VHDL modeling
• Generics, constant and open ports
• Test benches
• Combinational modules
• Tri-state buffers
• Decoders, multiplexors
• Priority encoder

• Laboratory 2 - VHDL Synthesis using MaxPlus II
• Combinational modules
continued
• Adders
• Parity checker
• Synchronous circuit design
• Synchronous sequential systems
• Modeling finite state machines

• Laboratory 3 - Keyboard Interface
• VHDL models of sequential units
• Latches, flip-flops
• Sequential circuit timing
• Timing exercises: fsm1.vhd  fsm3.vhd
• Exam 1 - Friday, January 28

• Registers, counters
• Algorithmic state machines
• Synthesis from ASM charts (one's counter exercise)
• Serial/parallel multiplier (multiplier VHDL)

• Laboratory 4 Divider Circuit or Train Lab
• Memory
• CPLDs and FPGAs

• Lab 5 Design Project
• Complex sequential systems
• Datapath/controller partitioning - dice game example
• CPU  - CPU Exercises

• VHDL simulation
• Event-driven simulation
• Simulation issues
• VHDL synthesis
• RTL synthesis
• Constraints and pitfalls
• Behavioral synthesis
• Exam 2

• Pipelining
• Testing digital systems
• Fault models
• Test pattern generation
• Fault simulation
• System design

• Design for Testability
• Structured design for test
• Built-in Self Test
• Boundary Testing
• Self-Timed Circuits

Final Exam: Monday, March 14, 1:00-3:00 PM

CT  12/2004