Syllabus
EE/CS 118/218 - Digital Design
Professor Traver
Winter, 2005
Course URL: http://doc.unon.edu/118
Texts:
-
Digital Systems Design with VHDL by Mark Zwoliński.,
Prentice Hall, 2000
-
Rapid Prototyping of Digital Systems, A Tutorial Approach,
James O. Hamblen, Michael D. Furman, Second Edition, Kluwer Academic Publishers,
2001
Topic Outline and Reading Assignments:
Week 1: Zwolinski, Chapters 1,2, 3
-
Digital Design Concepts
- Modern design process - tools, implementation choices
- CMOS technology
- Programmable logic - PLDs, CPLDs, gate arrays, FPGAs
- Electrical properties - noise margins, timing, fanout
-
Review combinational logic design
-
Minimization
-
Timing - logic hazards (Maxplus Exercise)
-
Number codes - 2's complement, fixed and floating point
-
Other codes - character, gray code, parity
- Combinational logic modeling with VHDL
- Overall structure - entity architecture
- Syntax - identifiers, spaces, comments
- Structural modeling - netlists
- Maxplus Exercise
Week 2: Zwolinski, Chapter 3,4Week 3: Zwolinski, Chapter 4,5
Week 4: Zwolinski, Chapters 5,6
Week 5: Zwolinski, Chapters 5,6
Week 6: Zwolinski, Chapter 6
Week 7: Zwolinksi, Chapter 7Week 8: Zwolinski, Chapter 8,9
- VHDL simulation
- Event-driven simulation
- Simulation issues
- VHDL synthesis
- RTL synthesis
- Constraints and pitfalls
- Behavioral synthesis
-
Exam 2
Week 9: Zwolinski, Chapter 10
-
Pipelining
-
Testing digital systems
-
Fault models
-
Test pattern generation
-
Fault simulation
-
System design
Week 10 Zwolinski, Chapter 11, 12
-
Design for Testability
- Structured design for test
-
Built-in Self Test
-
Boundary Testing
- Self-Timed Circuits
Final Exam: Monday, March 14, 1:00-3:00
PM
CT 12/2004