EE-154
VLSI Design
Homework Assignments

Week 1:
(problems 1-5 are from Chapter 1 reading)
1. What were the predecessor switching devices of the transistor?
2. How does CMOS compare to bipolar technology for digital circuits?
3. What have the growth rates been for IC and memory complexity over the last 25 years? Predict the integration complexity for ICs and memories for the year 2010.
4. What is the concept required to design complex chips with millions of gates? Give examples.
5. Why is it important for electrical and computer engineers to understand the operation of digital circuits at the device level?
6. Text problem 2.4
7. Text problem 2.5
8. Text problem 2.9
9. Text problem 2.13 

Week 2:
1. Appendix A, Exercise 1. (p 104)

2. Draw a cross section of the layout below for the two slices given, A and B.


 

3. Find the transistor diagram that corresponds to the layout in problem 2. 

Week 3:

Text problems: 3-1, 3-3, 3-4, 3-5, 3-7, 3-8a,b

Week 4:

Text Problems: 3-12, 3-13, 3-14, 3-15 


Week 5:
1. Find the transistor diagram of the XOR cell in the namin08 library. Discuss whether this is purely a complementary CMOS gate, a transmission gate, or something else.

2. Chapter 4 problems 1,2,3,4,5
Due Thursday.

Week 6: Text problems 4-6a,b, 4-13, 4-18, 4-22a,b,c,
 

Week 8:
1. Text problem 6.1

2. Use SPICE to find the propagation delay (clock to Q) of the following latches and flip-flops. Use a clock with rise and fall times of .5ns and measure both TpLH and TpHL. Use minimum size transistors except where the transistors must be sized for proper switching, and use the 1.2u process of the text.

a. Clocked SR (figure 6.13)
b. Clocked 6-transistor SR (figure 6.16)
c. Pseudostatic latch (figure 6.20)
d. C2MOS latch (figure 6.24)

Due Tuesday, October 30.

Week 9:

1. Analyze the LATPC element in the Tanner scmos library. The schematic can be found by opening the module in S-Edit.

a. Give the function table for the latch. Include the value of the internal node that is the input to the T16 and T17 transistors in the function table.
b. Is the latch static or dynamic? Justify your answer by explaining how memory is implemented in the latch.
c. Simulate the circuit with an output load capacitance of 7fF and inputs with .1ns rise and fall times to find the propagation delay from G to Q. How does this compare to the data sheet predicted delays below? Use the ami05.md models.

 TpHL = 125 + 1084*CL     TpLH = 139 + 1050*CL (picoseconds)

2. Find the clk-Q delay and the setup time for the D-flip flop in the AMI05 library. Use the 7fF load and .1ns rise and fall times as you did in problem 1.