EE-154/CS-154
VLSI Design

Course Objectives:

• Students will understand MOS transister operation including secondary effects of submicron devices.
• Students will understand CMOS circuit operation including static behavior (noise margins, switching thresholds, voltage swings) and dynamic behavior (propagation delays, power dissipation).
• Students will be able to analyze CMOS logic gates and understand logical, static and dynamic behavior.
• Students will be able to design CMOS logic gates using complementary CMOS, transmission gate and dynamic logic styles
• Students will understand the design issues involved in arithmetic circuits, particularly the adder.
• Students will be able to use modern EDA tools to design and analylze integrated circuits using manual layout, standard cells, and simulation.
• Students will be able to write a clear and consise technical report.

Text: Jan M. Rabaey, Digital Integrated Circuits - A Design Perspective,  Prentice-Hall, 1996

Week                         Subject                      Reading Assignment
_____________________________________________________________________________________
 1          Introduction                                  Chapter 1
            MOS(FET) transistor                           Section 2.3
_____________________________________________________________________________________
 2          Transistors and Layout                        Appendix A
                     Fabrication process, transistors     Silicon Run II Video    
                     Wires and vias, design rules           
                     Layout design and tools                 
_____________________________________________________________________________________
 3          The Inverter                                  Sections 3.1-3.3
                     Definitions and properties,
                     Static CMOS inverter behavior                                   
_____________________________________________________________________________________
 4          CMOS Logic Gates                              Sections 4.1-4.3
                     Static CMOS design,
                     Dynamic CMOS design
_____________________________________________________________________________________
 5          CMOS Logic Gates                              Sections 4.4
                     Power consumption,
                     Switching activity, low power design
                     MIDTERM 
______________________________________________________________________________________
 6          Sequential Circuits        
                     Static sequential circuits           Sections 6.1-6.3
                     Dynamic sequential circuits,         Section 6.5
                     Clocking strategies
_____________________________________________________________________________________
 7          Arithmetic Circuits                           Sections 7.2-7.5
                     Datapaths
                     Adders, Multipliers, Shifters 
_____________________________________________________________________________________
 8          Interconnects                                 Sections 8.1-8.5
                     Capactitive parasitics,                         
                     Resistive parasitics,
                     Inductive parasitics, packaging
_____________________________________________________________________________________
 9          Timing Issues                                 Sections 9.1-9.3
                     Clock skew, clocking styles,
                     Self-timed circuit design                      
_____________________________________________________________________________________
 10         Design Methodologies                          Sections 11.1-11.6
                     Kitchen timer chip                            
                     Review

Course Web Page: http://doc.union.edu/154
Check this site for homework assignments, notes, laboratories and other information.

Laboratories

There will be weekly and bi-weekly laboratory assignments. Laboratory work will take place in N108.

You should use a lab notebook for this course. Take notes as you do things so that you can easily refer to them later without wading through the long lab handouts.

You will write reports for most laboratories. Toward the end of the course you will work on a design project during lab time and submit a final report on this design.

Homework

Homework will be assigned approximately weekly and graded. Solutions will be made available.

Fabrication

Designs which are fully verified by simulation may be submitted to the MOSIS silicon foundry for fabrication. Unfortunately the first available run date is in January and it takes about 7 weeks for fabrication, so your chips will not be available until spring term.

Writing

This course is designated a W1 writing course in the Writing Across the Curriculum program. In addition to laboratory reports, one or two papers will be assigned based on outside readings. Writing will be reviewed carefully, corrected and in some cases rewrites may be necessary. Writing will be incorporated into the grade as specified below.

Grading

Homeworks                  10%
Laboratories and papers    15%   (15% writing)
Midterm                    30%
Project                    15%   (15% writing)
Final                      30%