EER-018
Introduction to Digital Computers
Lecture 14
Flip-Flops and Registers
Flip-flops
- Master-Slave flip-flop
- D-type master-slave
- Timing
- Edge-triggered flip-flop
- D-type edge-triggered flip-flop
- not transparent
- Timing
- Direct set and clear inputs
- JK flip-flop
- T flip-flop
Registers
- Storage register - parallel load: data inputs, data outputs, clk
- Shift register - serial load
- FIFO - first in, first out
- Parallel-Serial conversions
- SHR and ROR, SHL and ROL operations