EE-18 Exam 2 Outline
Fall, 2003

The exam will be on the following chapters: 5,6,8,9

Topics could include:

VHDL - entity, architecture, modeling with concurrent statements and with components and port map statements.

CMOS Logic Circuits

Logic Components: decoders, multiplexors, demultiplexors, half-adders, full-adders, parallel adders.

Binary Subtraction: 2's complement

Memory Elements: latches, flip-flops, SRAM, ROM