Introductory VLSI Courses

EDA Tools for Introductory VLSI Design Courses

Educational VLSI laboratory EDA tools vary from institution to institution, influenced by available hardware platforms, budgets for EDA tools and pedagogical goals. The following table lists the industrial tools most often used by academic institutions that fabricate student designs through MOSIS. Follow the link in the table to find more details on tool flows, libraries, system requirements, and links to University courses that use these tools.

	EDA Tool Flows
Operating System Platform	HDL and Chip Level: Functional Verification, RTL synthesis, mixed standard cell/custom blocks, floorplanning, block place and route	Logic and Physical Levels: Schematic capture, logic level simulation, standard cell place and route, custom layout, physical verification
Unix	Cadence (NC-Sim, BuildGates, Virtuoso) Mentor Graphics (ModelSim, Leonardo, IC Station) Synopsys (Design Compiler, Library Compiler)	Cadence (Composer, Verilog-XL,Virtuoso, Silicon Ensemble, Spectre) Mentor Graphics (Design Architect IC, IC Station, Quicksim II, Mach TA/Accusim II)
Windows	Tanner Research (L-Edit BPR)	Tanner Research ( S-Edit, L-Edit, LVS, T-Spice)

There are also some public domain and open source tools available. These tend to have limited functionality and support.

For a more complete list of EDA tools, please see http://www.mrc.uidaho.edu/vlsi/

Send comments and corrections to:

Cherrice Traver
Professor of Electrical and Computer Engineering
Union College
traverc@union.edu

Sponsored by the MOSIS Advisory Committee for Education
Richard Brown (chair), University of Michigan
Don Bouldin, University of Tennessee
Dale Edwards, SRC
Cesar Pina, MOSIS
Cherrice Traver, Union College