Logic and Physical Levels - Microsoft Windows Platforms -
Tanner Research
URL: http://www.tanner.com/
Basic tool flow:
Tool Definitions:
- S-edit - hierarchical schematic capture - logic and transistor
level
- L-edit - layout editor
- SPR - places and routes standard cells from cell library
- Extraction to spice file
- Design rule checking
- Cross section view of layout layers (great pedagogical tool)
- LVS - Layout vs Schematic verification tool
- T-Spice - circuit simulator
System Requirements: Microsoft® Windows 2000, Windows NT
4.0 (Service Pack 3 or greater), Windows 98/ME, Windows XP Pentium II (or
better) class of Intel® processor, 350 MHZ or better Windows 98/ME -
64 MB RAM
Libraries: MOSIS standard cell and pad libraries (MOSIS or AMI Design
Kits) available, purchased separately.
Licensing: Node locked (hardware key) or floating licenses via
a license server
Educational Program Contact:
Debra Knight
Tanner EDA
(877) 325-2223 x 5975
debra.knight@tanner.com
Courses using Tanner tools: