Phased logic (PL) is a design methodology and circuit architecture that allows designers to specify synchronous systems and then translate them to self-timed, delay-insensitive implementations. Designs are specified in VHDL RTL and synthesized by the Synopsys Design Compiler to a netlist of D flip-flops and 4-input logic gates. This netlist is translated to a netlist of phased logic gates that operate correctly without a global clock. A tutorial is available that illustrates the process for a simple 2-bit counter.

In a phased logic system, the phased logic gates have the following properties:

• Delay-insensitive at the borders using LEDR inputs and outputs
• Internal phase bit that toggles when phase of all inputs matches internal phase
• Implementation-dependent internal delay constraints
• The following inputs and outputs
• Function output (vo, to)
• Inverted phase function output (vo, tob) to allow for configuration as barrier or through gate
• Feedback output (fo) (equal to gate phase)
• Inverted feedback output (fob)
• Reset input
• Sets internal phase to a set phase (we will use even)
• For barrier gates that implement synchronous functions, the output must be set to a particular value (set or reset) during reset, this  implies "set" or "clear" type inputs, or a "reset value" input, in addition to the reset.
• Feedback inputs connected to completion tree that delays gate firing until all feedback inputs are the same phase as the internal phase

This research is in cooperation with Mississippi State and Southern Methodist University. The focus of the work done at Union is to investigate PL gate designs that optimize power and performance, to verify gate designs, and to develop new gate designs for token flow control and phase multiplication and division. 

Previous Work - SRAM-based Programmable Phased Logic Gate Implementation
Based on the design in Linder's dissertation [1], this implementation allows for reconfigurable phased logic systems if extended to a complete FPGA architecture. The 4-input cell uses dynamic logic and an SRAM for the compute function. Tspice^TM from Tanner Research was used for all spice simulations. 

• Original layout from [1] .
• Hierarchical circuit diagrams and spice models of gate .
• Results of spice simulations for power calculations
• Results of spice simulations for delay calculations

• Gate schematic
• Standard cell layout
• Spice simulation power and delay results
• Chip layout
  

• Gate schematic
• Master gate schematic
• Trigger gate schematic
  
• Standard cell layout
• Spice simulation power and delay results
• Chip layout
  

Using ATACS for Verification of Hazard-Freedom of Phased Logic Wrappers

[3] R. Reese, and C. Traver, "Synthesis and Simulation of Phased Logic Systems", Technical Report MSSU-COE-ERC-00-09, MSU/NSF Engineering Research Center, June 2000. Presented at  International Workshop on Logic Synthesis (IWLS 2000), Dana Point, CA, June 2, 2000. Also available for download at http://www.erc.msstate.edu/labs/mpl/projects/phased_logic/yr2000results/newmapping.pdf .

[5] R. B. Reese, M. A. Thornton, and C. Traver, “ Arithmetic Logic Circuits using Self-timed Bit-Level Dataflow and Early Evaluation”, Proceedings of the 2001 Conference on Computer Design, September 2001, pp 18-23.