*********************col_cell***********************
*One column decoder cell. Instantiates two decoder cells, two
*inverters (like the row_cell), and a 2 to 1 multiplexor implemented
*as in figure 5.5.
*MUX Transistors and decoder instances from colDec.N file:
*	TN oddPullDown w=1200 l=200 g=32 s=24 d=18;
*	TN evenPullDown w=1200 l=200 g=33 s=23 d=16;
*	TN oddNotPullDown w=1200 l=200 g=32 s=26 d=17;
*	TN evenNotPullDown w=1200 l=200 g=33 s=25 d=15;
*	TP evenPrecharge w=1700 l=200 g=19 s=21 d=23;
*	TP oddPrecharge w=1700 l=200 g=20 s=21 d=24;
*	TP oddNotPrecharge w=1700 l=200 g=20 s=21 d=26;
*	TP evenNotPrecharge w=1700 l=200 g=19 s=21 d=25;
*	TP evenBleeder w=300 l=650 g=22 s=21 d=23;
*	TP oddBleeder w=300 l=650 g=22 s=21 d=24;
*	TP oddNotBleeder w=300 l=650 g=22 s=21 d=26;
*	TP evenNotBleeder w=300 l=650 g=22 s=21 d=25;
*	TN inv2PullDown w=1200 l=200 g=4 s=29 d=3;
*	TN inv1PullDown w=1200 l=200 g=27 s=29 d=4;
*	TP inv2PullUp w=1600 l=200 g=4 s=28 d=3;
*	TP inv1PullUp w=1600 l=200 g=27 s=28 d=4;
*	INST colDec_G_evenDec evenDecoder decoderOutput=33 gndTop=11
*	 gndBot=11 vddTop=12 vddBot=12 evenPrechargeTop=13
*	 evenPrechargeBot=13 oddPrechargeTop=14 oddPrechargeBot=14 x1Top=3 
*	 x1Bot=3 x1NotTop=4 x1NotBot=4 x0Top=1 x0Bot=1
*	 x0NotTop=2 x0NotBot=2 oddGndTop=10 oddGndBot=10 evenGndTop=9
*	 evenGndBot=9 y1Top=7 y1Bot=7 y1NotTop=8 y1NotBot=8
*	 y0Top=5 y0Bot=5 y0NotTop=6 y0NotBot=6;
*	INST colDec_G_oddDec oddDecoder decoderOutput=32 gndTop=11
*	 gndBot=11 vddTop=12 vddBot=12 evenPrechargeTop=13
*	 evenPrechargeBot=13 oddPrechargeTop=14 oddPrechargeBot=14 x1Top=3 
*	 x1Bot=3 x1NotTop=4 x1NotBot=4 x0Top=1 x0Bot=1
*	 x0NotTop=2 x0NotBot=2 oddGndTop=10 oddGndBot=10 evenGndTop=9
*	 evenGndBot=9 y1Top=7 y1Bot=7 y1NotTop=8 y1NotBot=8
*	 y0Top=5 y0Bot=5 y0NotTop=6 y0NotBot=6;
.include ./ml2_125.md
.include ./decoderc.spc
.subckt col_cell PrechargeOdd  y1odd x0odd y0odd x1odd oddOut
+PrechargeEven y1even x0even y0even x1even evenOut colInput
+cin cinnot even odd oddNot evenNot evenNotRam oddNotRam oddRam
+evenRam Vdd 0
*Decoder cells, as in row decoder
xdecoderOdd co PrechargeOdd y1odd x0odd  y0odd x1odd oddOut Vdd 
+0 decoderc
xdecoderEven ce PrechargeEven y1even x0even y0even  x1even evenOut Vdd
+0 decoderc
*Inverters to buffer input
Minv1pullup cinnot colInput Vdd Vdd pmos w='16*lambda' l='2*lambda'
Minv1pulldown cinnot colInput 0 0 nmos w='12*lambda' l='2*lambda'
Minv2pullup cin cinnot Vdd Vdd pmos w='16*lambda' l='2*lambda'
Minv2pulldown cin cinnot 0 0 nmos w='12*lambda' l='2*lambda'
*Multiplexor transistors:
* Nmos transistors controlled by column decoder outputs
ModdPullDown odd co oddRam 0 nmos w='12*lambda' l='2*lambda' 
MevenPullDown even ce evenRam 0 nmos w='12*lambda' l='2*lambda'
ModdNotPullDown oddNot co oddNotRam 0 nmos w='12*lambda' l='2*lambda'
MevenNotPullDown evenNot ce evenNotRam 0 nmos w='12*lambda' l='2*lambda'
* Pmos transistors controlled by precharge inputs from control
MevenPrecharge evenRam PrechargeEven Vdd Vdd pmos w='17*lambda' l='2*lambda'
ModdPrecharge oddRam PrechargeOdd Vdd Vdd pmos w='17*lambda' l='2*lambda' 
ModdNotPrecharge oddNotRam PrechargeOdd Vdd Vdd pmos w='17*lambda' l='2*lambda'
MevenNotPrecharge evenNotRam PrechargeEven Vdd Vdd pmos w='17*lambda' l='2*lambda'
* Weak pmos transistors to hold precharge?
MevenBleeder evenRam 0 Vdd Vdd pmos w='3*lambda' l='6.5*lambda' 
ModdBleeder oddRam 0 Vdd Vdd pmos w='3*lambda' l='6.5*lambda'
ModdNotBleeder oddNotRam 0 Vdd Vdd pmos w='3*lambda' l='6.5*lambda'
MevenNotBleeder evenNotRam 0 Vdd Vdd pmos w='3*lambda' l='6.5*lambda'
.ends