*********************col_decoder.spc***************************** *The full 4-cell column decoder. Each cell icludes decoders, 2 *inverters and a mux. Two pull-down transistors are shared by all cells * * Decoder inputs are connected as follows: * y1 x0 y0 x1 * cell 0 odd st4 sv4not sv3not st3 * cell 0 even st4not sv4not sv3not st3not * cell 1 odd st4 sv4not sv3 st3not * cell 1 even st4not sv4not sv3 st3 * cell 2 odd st4not sv4 sv3not st3 * cell 2 even st4 sv4 sv3not st3not * cell 3 odd st4not sv4 sv3 st3not * cell 3 even st4 sv4 sv3 st3 * * st and sv signals are generated by the following cells: * * cell 0 sv3 sv3not * cell 1 st3 st3not * cell 2 sv4 sv4not * cell 3 st4 st4not .include ./col_cell.spc .subckt col_decoder evenNot0 oddNot0 odd0 even0 evenNot1 oddNot1 odd1 +even1 evenNot2 oddNot2 odd2 even2 evenNot3 oddNot3 +odd3 even3 sv3in st3in sv4in st4in even evenNot odd oddNot PrechargeEven +PrechargeOdd Vdd 0 xcell0 PrechargeOdd st4 sv4not sv3not st3 oddOut PrechargeEven st4not +sv4not sv3not st3not evenOut sv3in sv3 sv3not even odd oddNot evenNot +evenNot0 oddNot0 odd0 even0 Vdd 0 col_cell xcell1 PrechargeOdd st4 sv4not sv3 st3not oddOut PrechargeEven st4not +sv4not sv3 st3 evenOut st3in st3 st3not even odd oddNot evenNot +evenNot1 oddNot1 odd1 even1 Vdd 0 col_cell xcell2 PrechargeOdd st4not sv4 sv3not st3 oddOut PrechargeEven st4 +sv4 sv3not st3not evenOut sv4in sv4 sv4not even odd oddNot evenNot +evenNot2 oddNot2 odd2 even2 Vdd 0 col_cell xcell3 PrechargeOdd st4not sv4 sv3 st3not oddOut PrechargeEven st4 +sv4 sv3 st3 evenOut st4in st4 st4not even odd oddNot evenNot +evenNot3 oddNot3 odd3 even3 Vdd 0 col_cell * * Shared SeriesGnd transistors MseriesGndodd oddOut PrechargeOdd 0 0 nmos w='16*lambda' l='2*lambda' MseriesGndeven evenOut PrechargeEven 0 0 nmos w='16*lambda' l='2*lambda' * .ends