*Subcircuit of control module. (upper and middle left circuits in
*Figure 5.6) At the top level, inputs are reset, e, e', o, o', en, on'
*and outputs are xv, xv', xt, xt'. 
.include ./ml2_125.md
.subckt contX pul pur pdl pdr reset latoutnot latout bleedout Vdd 0
* from nControl
Mpdl bleedout pdl 0 0 nmos l='2*lambda' w='8*lambda' 
Mpdr bleedout pdr 0 0 nmos l='2*lambda' w='8*lambda' 
* from pControl
Mpul bleedout pul Vdd Vdd pmos l='2*lambda' w='12*lambda'
Mpur bleedout pur Vdd Vdd pmos l='2*lambda' w='12*lambda'
* from nInv
MpdlI latoutnot bleedout 0 0 nmos l='2*lambda' w='12*lambda'
MpdrI latout latoutnot 0 0 nmos l='2*lambda' w='12*lambda'
Mbldn bleedout latoutnot latout 0 nmos l='8*lambda' w='3*lambda'
* from pInv
MudlI latoutnot bleedout Vdd Vdd pmos l='2*lambda' w='16*lambda'
MudrI latout latoutnot Vdd Vdd pmos l='2*lambda' w='16*lambda'
Mbldp bleedout latoutnot latout Vdd pmos l='8*lambda' w='3*lambda'
* reset transistor
Mres bleedout reset 0 0 nmos l='2*lambda' w='4*lambda'
.ends