* Spice model for Programmable Gate (Figure 5.2)
.include ./col_decoder.spc
.include ./row_decoder.spc
.include ./ramArray.spc
.include ./control.spc

xcontrol xv xvn xt xtn sf reset pe po e o on en  Vdd 0 control
xramArray ro0 ro1 ro2 ro3 re0 re1 re2 re3 en0 en1 en2 en3 on0
+on1 on2 on3 o0 o1 o2 o3 e0 e1 e2 e3 wx0 wx1 wx2 wx3 wxn0 wxn1 wxn2
+wxn3 dx0 dx1 dx2 dx3 Vdd 0 ramArray
* check to see if row and column decoders share nTrans_G ?
xrowdec st2 sv2 st1 sv1 ro0 re0 ro1 re1 ro2 re2 ro3 re3 pe po
+Vdd 0 row_decoder
xcoldec en0 on0 o0 e0 en1 on1 o1 e1 en2 on2 o2 e2 en3 on3
+o3 e3 sv3 st3 sv4 st4 e en o on pe po Vdd 0 col_decoder
.include ./lut4.cmd
.end