**********************ramBit.spc*************************************
*A single ram bit cell. Follows directly from ramBit.N file.
*
*	TN inv1PullDown w=1200 l=200 g=12 s=10 d=13;
*	TN evenNotPullDown w=1200 l=200 g=1 s=13 d=8;
*	TN inv2PullDown w=1200 l=200 g=13 s=10 d=14;
*	TN evenPullDown w=1200 l=200 g=1 s=14 d=6;
*	TN dataPass w=400 l=200 g=2 s=4 d=12;
*	TN holdPullDown w=400 l=200 g=3 s=14 d=12;
*	TN oddNotPullDown w=1200 l=200 g=5 s=13 d=9;
*	TN oddPullDown w=1200 l=200 g=5 s=14 d=7;
*	TP inv1PullUp w=400 l=200 g=12 s=11 d=13;
*	TP inv2PullUp w=400 l=200 g=13 s=11 d=14;
*	TP holdPullUp w=400 l=200 g=2 s=14 d=12;
* 1=re, 2=wx, 3=wxn, 4=dx, 5=ro, 6=e, 7=o, 8=en, 9=on, 10=0, 11=Vdd
* There was an inconsistency in this model with Figure 5.4 and the .N
* file seems incorrect as given above. Nodes 12, 13 and 14 were changed
* in some places, noted below.
.include ./ml2_125.md
.subckt ramBit ro re en on o e wx wxn dx Vdd 0
Minv1pd 13 14 0 0 nmos w='12*lambda' l='2*lambda'	;changed gate node
Mevennotpd en re 13 0 nmos w='12*lambda' l='2*lambda'
Minv2pd 14 12 0 0 nmos w='12*lambda' l='2*lambda'	;changed gate node
Mevenpd e re 14 0 nmos w='12*lambda' l='2*lambda'	
Mdatapass 12 wx dx 0 nmos w='4*lambda' l='2*lambda'
Mholdpd 12 wxn 13 0 nmos w='4*lambda' l='2*lambda'	;changed source node
Moddnpd on ro 13 0 nmos w='12*lambda' l='2*lambda'
Moddpd o ro 14 0 nmos w='12*lambda' l='2*lambda'
Minv1pu 13 14 Vdd Vdd pmos w='4*lambda' l='2*lambda'	;changed gate node
Minv2pu 14 12 Vdd Vdd pmos w='4*lambda' l='2*lambda'	;changed gate node
Mholdpu 12 wx 13 Vdd pmos w='4*lambda' l='2*lambda'     ;changed source node
.ends