***********************row_decoder.spc******************************
* The full 4-cell row decoder. Each cell includes decoders and 2 inverters.
* 2 pull-down transistors are shared by all cells
*
* Decoder inputs are connected as follows:
*		 y1	       x0	       y0	x1
* cell 0 odd	 st2	       sv2not	       sv1not	st1
* cell 0 even	 st2not	       sv2not	       sv1not	st1not
* cell 1 odd	 st2	       sv2not	       sv1	st1not
* cell 1 even	 st2not	       sv2not	       sv1	st1
* cell 2 odd	 st2not	       sv2	       sv1not	st1
* cell 2 even	 st2	       sv2	       sv1not	st1not
* cell 3 odd	 st2not	       sv2	       sv1	st1not
* cell 3 even	 st2	       sv2	       sv1	st1
*
* st and sv signals are generated by the following cells:
*
* cell 0 st2 st2not
* cell 1 sv2 sv2not
* cell 2 st1 st1not
* cell 3 sv1 sv1not
.include ./row_cell.spc
.subckt row_decoder st2in sv2in st1in sv1in ro0 re0 ro1 re1 ro2 re2 ro3 re3
+PrechargeEven PrechargeOdd Vdd 0

xcell0 ro0 PrechargeOdd st2 sv2not sv1not st1 oddOut re0 PrechargeEven
+ st2not sv2not sv1not st1not evenOut st2in st2 st2not Vdd 0 row_cell 

xcell1 ro1 PrechargeOdd st2 sv2not sv1 st1not oddOut re1 PrechargeEven
+ st2not sv2not sv1 st1 evenOut sv2in sv2 sv2not Vdd 0 row_cell  
xcell2 ro2 PrechargeOdd st2not sv2 sv1not st1 oddOut re2 PrechargeEven
+ st2 sv2 sv1not st1not evenOut st1in st1 st1not Vdd 0 row_cell  
xcell3 ro3 PrechargeOdd st2not sv2 sv1 st1not oddOut re3 PrechargeEven
+ st2 sv2 sv1 st1 evenOut sv1in sv1 sv1not Vdd 0 row_cell  
*
* Shared SeriesGnd transistors - to be moved up in hierarchy later
MseriesGndodd oddOut PrechargeOdd 0 0 nmos w='16*lambda' l='2*lambda'
MseriesGndeven evenOut PrechargeEven 0 0 nmos w='16*lambda' l='2*lambda'
*
.ends